In the semiconductor industry, it is known to form nFETs and pFETs on semiconductor substrates that contain various heterolayers. Such technology is described, for example, in A. Sadek, et al. “Design of Si/SiGe Heterojunction Complementary Metal-Oxide-Semiconductor Transistors”, Electron Devices, IEEE Transactions, Vol. 43, Issue 8, August 1996, pp. 1224-1232. Specifically, an optimized Si/SiGe heterostructure for CMOS transistor operation is provided in the A. Sadek, et al. article which has a planar design and avoids inversion of the Si layer at the oxide interface.
In such technology, the basic idea is to form a plurality of layers in a single structure, and then fabricate nFET and pFET channels in their respectively optimal material layer. For example, tensile-strained Si for nFETs and compressive-strained SiGe for pFETs. This is usually achieved in the prior art by either etching away unnecessary layers in selective areas, or by growing layers in selective areas.
One evolution of the foregoing is to fabricate a structure that consists of multiple semiconductor layers and insulator layers such as semiconductor layer 2/ insulator 2/ semiconductor 1/ insulator 1/ substrate. Some devices, e.g., nFETs, pFETs or a combination thereof, can be fabricated in semiconductor layer 1, while other devices can be fabricated in semiconductor layer 2. Since both semiconductor layers are located on an insulator, the devices formed thereon will be SOI FETs.
One problem with the foregoing approaches is that there exists a step region (consisting of the various semiconductor layers) between the different types of device structures. This is especially prevalent in the semiconductor/insulator/semiconductor structure where it is preferred that the insulator layers be at least several hundred Angstroms thick.
The foregoing thickness requirement is needed to provide devices that have minimal junction capacitance. Hence, a tradeoff exists between the junction capacitance and the step height between different types of semiconductor devices. For instance, in a structure that consists of semiconductor 2, insulator 2, semiconductor 1, and insulator 1 layers stacked in order, the junction capacitance of the FETs fabricated on the semiconductor 2 is strongly influenced by the thickness of the insulator 2 layer. In order to minimize the junction capacitance and to realize higher circuit speed, the insulator 2 layer needs to be thick. On the other hand, the thickness of the insulator 2 layer adds to the step height between semiconductor 1 and semiconductor 2. For optimal integration of high density circuits, this step height (and thus the thickness of the insulator 2 layer) needs to be as small as possible.
There is thus a need for providing a semiconductor structure in which SOI MOSFETs are formed on a plurality of semiconductor layers such that the step height between the various devices is substantially reduced, without penalizing the junction capacitance of the device fabricated on the upper semiconductor layer.